Adaptive and Dynamic Stability Enhancement for Memories

ABSTRACT

Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

FIELD

The present invention pertains to the field of memory cell read/writeassist control circuitry, and in particular to a compensating scheme forsensed memory cell conditions in a read/write assist system.

BACKGROUND

SRAM (Static Random Access Memory) is a form of volatile memory commonlyused for short term, high speed storage. SRAM offers high speed inexchange for high cost and high power consumption compared to many othermemory types. It is frequently used as cache memory in processors ofmany different types, such as central processing units, graphicsprocessors, and controllers. It is also used for caches and buffers incommunications interfaces, video interfaces, and signal processors. SRAMis frequently integrated onto the same die with a processor andtherefore fabricated using the same technologies, such as CMOS(Complementary Metal Oxide Semiconductor).

As processing circuitry shrinks and operates at lower power, the designmargin for SRAM continues to shrink. SRAM bitcells have been producedsmaller than 0.1 μm² using 22 nm technology. The consistency and yieldof SRAM arrays, however, has declined. In part this is due to increasedvariation in produced dies. As the components on the die shrink, thesame production variations become larger in comparison to thecomponents. These variations mean that some SRAM cells have a higherminimum operating voltage than others on the same die. The reduced sizeand reduced operating voltages have also reduced the difference betweenthe read voltage and the write voltage.

Die to die variations (variations between dies produced at the same timeon a single wafer) result in some dies being limited by a minimum readvoltage, while other dies are limited by a minimum write voltage. A slowN (N-type MOS (Metal Oxide Semiconductor) switching voltage) fast P(P-type MOS switching voltage) die would be write limited while a fast Nslow P die would be read limited. Operating temperature also affects thecharacteristics of each die. Many die that are write limited at coldtemperatures may be read limited at hot temperatures.

Word-Line Under-Drive (WLUD) has been proposed to improve the V_(CCmin)(minimum operating voltage or Common-Collector Voltage) margin of amemory bitcell. Under-driving the word-line during memory access reducesthe effective gate drive thus enhancing read stability. However, WLUDdegrades cell writabilty and so increases V_(CCmin) for writeoperations. In addition, due to the die to die variations and variationswithin a particular die, the best WLUD to use for different SRAMbitcells or SRAM arrays can be very different. For dies that arefabricated on different wafers, the differences can be still greater.For best performance, each die is characterized independently, howeverthis adds to the production test-time and cost. Shifts in read/writebalance due to temperature changes will also have to be characterized.This further increases test-time. In addition, a read-write assistsetting will have to chosen that helps meet goals at both low and hightemperatures.

Smart and adaptive assist circuits have been introduced to open up thedesign margin as well as to meet power and performance specifications.V_(CC) scaling is especially important to meet the increasinglystringent power requirements. Although read stability is a major factorlimiting voltage scaling for high density SRAM cells, the design windowbetween read stability and the write margin is steadily decreasing and asignificant number of SRAM cells can be write limited in a high volumemanufacturing environment.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention aredescribed with reference to the following figures, wherein likereference numerals refer to like parts throughout the various viewsunless otherwise specified.

FIG. 1 is a diagram of a six transistor SRAM cell to which embodimentsof the invention may be applied.

FIG. 2 is a diagram of an example on-die sensor according to anembodiment of the present invention.

FIG. 3 is a diagram of an example controller module coupled to sensorsof the type shown in FIG. 2 according to an embodiment of the presentinvention.

FIG. 4 is a diagram of an example word-line under-drive and read/writecircuit coupled to the controller of FIG. 3 according to an embodimentof the present invention.

FIG. 5 is diagram of simulated waveforms on a common timing axis to showthe operation of a word-line under-drive circuit according to anembodiment of the present invention.

FIG. 6 is a computer system incorporating features of FIGS. 2, 3, and 4according to an embodiment of the invention.

DETAILED DESCRIPTION

An adaptive control system can adjust read/write settings of a memoryread/write system based on inputs from a sensor on the memory. In oneembodiment, an adaptive SRAM word-line under-drive (AWLUD) approach canuse a bitcell-based sensor to dynamically optimize the strength of theWLUD for each die. A blanket application of WLUD improves V_(CCmin) forread-limited dies yet also significantly degrades V_(CCmin) andperformance for write-limited dies. By selectively applying WLUD, thebenefit of WLUD can be substantially improved. An on-die sensor can beused to classify the die as read or write-limited and a programmableswitch can be used to apply the optimal WLUD strength for eachindividual die. In addition, a die can shift from being write-limited toread-limited with temperature. The sensor can be used to tracktemperature and process variations, allowing dynamic adjustment of WLUDstrength for each die to improve the V_(CCmin) distribution.

In one embodiment, a small PMOS transistor is embedded in each word-linedriver and then shared among the 256-row word-line drivers of an arrayto reduce the area occupied by the PMOS transistor. In one embodiment, asensor output for an array of SRAM bitcells is converted to digitalcontrol bits to provide programmability. The sensor tracks temperatureand adaptively changes the read-assist setting. The sensor can alsotrack process skew, voltage, temperature and aging.

FIG. 1 shows an example six transistor SRAM cell 10 to which embodimentsof the present invention may be applied. Embodiments of the presentinvention may also be applied to variation and modification of this cellas well as to other types of SRAM cells including eight, ten or moretransistor cells. The cell has two cross-coupled inverters 12, 14 thatstore one of two different states designated as 0 and 1 or low and high.A first access transistor 16 connects to a bitline (BL) to provide thestored state when a read of the memory is performed. A second accesstransistor 20 connects to an inverted bit line 22 to provide theopposite of the stored state. This line is optional and is typicallyused for differential signaling.

The cell can be accessed through the access transistors by enabling theword-line (WL) 24. During reads, the bit lines are driven low and highby the cross-coupled inverters and are read by differential sensecircuitry. During writes, the bit lines are driven high and low by anexternal voltage applied to the bit lines when the word-line is enabled.This voltage is set to be high enough that it overrides the voltagesstored in the inverters.

A word-line under-drive system reduces the voltage on the word-line 24during memory access. This reduces the effective gate drive voltageenhancing stability of the inverter states while they are being read.Under driving the WL reduces the required voltage (V_(CCmin)) 26 for thecell during reads, but increases the required voltage for the cellduring writes. The optimal amount of word-line under-drive (WLUD)differs for different SRAM cells due to production variation,temperature shifts and aging. These variations can be compensated byadapting the word-line under voltage to the conditions of the particularbitcell. Such an adaptation can be implemented, in part, by using asensor as shown in FIG. 2.

The on-die sensor 30 of FIG. 2 can be used to classify the die uponwhich it is located as read or write-limited. The sensor can tracktemperature and process variations, allowing dynamic adjustment of theWLUD strength for each die to improve the V_(CCmin) characteristics forthe die. The sensor is built to resemble the SRAM cells of the same die.In this example it is based on a six transistor SRAM cell, similar tothat of FIG. 1. If the memory array uses 2, 4, 8, 10 transistor or anyother configuration, then the sensor can be redesigned appropriately. Inone embodiment, the sensor is incorporated into a die in or near an SRAMbitcell array. Preserving the bitcell layout and location causes thesensor to more closely measure the conditions for actual SRAM cells. Thebehavior of the sensor depends, in part, on the layout of the circuit.

Because the sensor is located on the die near or among the cells of thememory array, it will also age in the same way as the memory cells.Aging is automatically tracked by the sensor regardless of a any initialprogramming. The read assist signal, which is controlled, at least inpart, by the sensor, is accordingly corrected as the circuit ages.

The sensor can be simultaneously shared across multiple subarrays. Toprovide a more generalized view of the sensed voltage, multiple sensorscan be coupled in parallel. This will allow the voltage reading fromeach sensor to be averaged across all of the other connected sensors.So, for example in a 256 kilobit memory sub-array, there may be 50 to100 sensors spread throughout the subarray coupled in parallel toprovide an average voltage across the sub-array. The best number ofsensors and their specific placement throughout a sub-array can beadapted to suit different memory array sizes and topologies.

Alternately, a different sensor can be used in each subarray. However,this may result in larger random variation because a sensor modeledafter the layout of a single SRAM cell is not big enough to average outthe variations between cells and subarrays in a single array.Alternatively, using a relatively larger centralized sensor locatedoutside of the subarray can allow random variations to be mitigatedwhile the area overhead is minimized because the sensor is shared amongtens of subarrays.

In FIG. 2, the SRAM cell of FIG. 1 has been modified to convert it intoa sensor cell. The lower transistors of both inverters 12, 14 aredisconnected from the corresponding upper transistors. The lowertransistors are tied to ground V_(SS) at their drains and thedisconnected sources are left to float. The gates of the lowertransistors are each coupled to the corresponding gate of the uppertransistor of each inverter as in FIG. 1. These gates are all alsocoupled to ground. The cross coupling between the inverters is alsobroken. The internal nodes are shorted to each other directly andconnected to a V_(sensor) output 32. The gates of the access transistors16, 18 are no longer tied to a word-line but to V_(CC) together with thesources of the upper transistors of the inverters. The bitline nodes ofthe access transistors are grounded.

In operation, the sensor, as shown in FIG. 2, has multiple pull-up PMOStransistors and multiple pass-gate NMOS transistors in a seriesconnection. The ratio of the voltage of the pull-up PMOS and pass-gateNMOS determines the sensor output voltage, V_(sensor). The V_(sensor)voltage has a strong correlation to the write margin for the SRAM andtherefore can be used to adjust the parameters of a read/write assistcircuit. In one example, the sensor output can be used to turn a WLUD onor off. The sensor will track these P/N ratio shifts regardless ofcause. The causes can include temperature changes, process skews, aging,supply voltage, and any other factors that affect the performance of thememory cells.

A variety of other electrical parameters can be measured instead or inaddition to the P/N ratio shown and described in FIG. 2. For example asensor node at a pull-down/pass-gate junction may be used to provide anN/N ratio. Other ratios may also be used instead or in additiondepending on the particular application.

While several of the transistors of the sensor can be eliminated orsubstituted with simpler components without changing the electricalfunction of the circuit, these changes will affect the layout of theparts on the die. By closely following the layout of an SRAM bitcell,the sensor more closely follows the behavior of nearby SRAM bitcells.Multiple sensor cells 34, 36, etc. on the same die or in the same arrayor subarray can be connected in parallel to give a good average valuefor the sensor voltage.

The sensor output is applied to a controller module 40 shown in FIG. 3.In one embodiment, a plurality of sensors are coupled in parallel toeach other and the averaged voltage is coupled to a single controllermodule. For a single array, there may be multiple sensors on eachsubarray and a single controller for the entire array. Alternatively,there may be a single controller for multiple arrays, or a controllerfor each subarray.

The controller has a comparator block with two comparators 42, 43. Oneinput to each comparator is the sensor output voltage 32 and the otheris a reference voltage Vref1 44, Vref2 45. The first comparator 42, isconfigured to produce an output 46 only if the sensor voltage is lessthan the first reference voltage (Vsensor is <Vref1). This firstcomparator output 46 can be used to turn on a switch on a WLUD circuitdescribed below. For other types of read/write assist systems, thesensor can be used to turn on or adjust a different setting. In theexample circuit, this output will allow a strong WLUD to be applied tothe corresponding SRAM bitcell word lines. The second comparator willturn on its output 47, only if the sensor voltage is less than a secondreference voltage (Vsensor<Vref2). This turns on a different switch ofthe WLUD circuit which reduces the voltage of the WLUD.

In the illustrated example, the comparators turn on when Vsensor is lessthan the corresponding threshold. Also in this example Vref2>Vref1. Thisprovides these 3 states as Vsensor increases: In state 1,Vsensor<Vref1<Vref2. In state 1, P3 and P4 are both on. As Vsensorincreases, the system reaches state 1. In state 2, Vref1<Vsensor<Vref2.As a result, P3 is on and P4 is off. If Vsensor increases further, thenthe system can enter a third state. In this state, Vref1<Vref2<Vsensor.In other words, Vsensor is greater than both thresholds. In this stateboth P3 and P4 are off.

The comparators naturally have an offset due to production variationsthat can contribute to the overall error in the system. This error canbe compensated by adjusting the reference voltages Vref1, Vref2. In theillustrated example, each reference voltage 44, 45 is generated by ageneration circuit 50, 51. The generation circuits each have a voltagedivider 52, 53 and a multiplexer 54, 55 each with a bias input 56, 57for programming. The voltage divider can be configured with a string ofresistors with connection nodes between each one (only two resistors areshown in FIG. 3, however more may be used for higher precision). Any oneof the different voltage values can be chosen after the circuit is builtby making a connection from an appropriate node. Because the voltage ofa voltage divider is determined by the ratio of the resistances aboveand below the node, the divider provides reference voltages that areindependent of process variations and temperature.

While voltage dividers, bias input, and comparators are shown, thegeneration of control signals into the read/write circuit of FIG. 4 canbe done in a variety of different ways. The voltage can be converted todigital and applied to logic circuits. The voltage sensor can be coupledto diode-connected transistors, etc. The particular control system canbe selected to suit any particular application.

After a die is fabricated, it is typically characterized, tested andcalibrated. During characterization, optimal values can be determined toset Vref1 and Vref2. All of the dies on a wafer can typically beprogrammed with the optimum values. In a high-volume manufacturingenvironment, the test time to set the reference voltage values may bereduced compared to die-by-die programming. Initially, there mayseparate read/write V_(CCmin) characterizations. Once the processcharacterization is complete and the Vref settings are determined, theadaptive WLUD circuits allow for rapid testing. After the initialcharacterization cost, the test time may be substantially reducedcompared to die-by-die programming. Using the WLUD circuits describedbelow, die by die measurements are not necessary because the WLUDcircuit will be controlled on and off based on the controller referencevoltages and the sensor input.

The reference voltages 44, 45 are applied to comparators 42, 43 forcomparison against the sensor voltage 32. The sensor voltage, in thisway is converted to two different on, off signals 46, 47. The analogsensor voltage is therefore quantized into digital control signals. Thequantization is adjustable using the configurable voltage dividers andthe adjustable bias inputs into the voltage reference generatorcircuits. Additional comparators can be coupled to additional or thesame reference voltage circuits to provide additional quantized signals.

The comparator outputs are fed to an adaptive dynamic WLUD circuit 60such as the example shown in FIG. 4. The WLUD controller 40 of FIG. 3,through the comparator outputs 46, 47 adjusts the strength of the WLUDapplied to the SRAM bitcell word lines 24. In one example, there is aseparate WLUD circuit 60, 61, 62, etc. for each subarray. Each subarraymay be a part of e.g. a 16 kB array. The comparator outputs act ascontrol signals for all of the WLUD circuits of the array. A singlecontroller can control many WLUD circuits. In one example, there is onecontroller for the array one, a set of sensors for each subarray and oneWLUD circuit for each cell of the array. FIG. 4 shows multiple WLUDcircuits for each subarray, for example 256, one for each SRAM bitcell.Accordingly, the final stage WL drivers 64, 65 are indicated as WL<0> toWL<255>.

The word-line under-drive circuit reduces the voltage provided by aword-line drive circuit. The word-line drive circuit produces aword-line drive voltage at its outputs. The outputs 64 for the wordlines are taken at the junction 66 between a drain 68 and a source 70 oftwo transistors of an inverter 72. The inverter is coupled betweenV_(CC) and V_(SS) and has an inverted p-type and an n-type transistor inseries, the gates of which are coupled to a common timing reference 74.Such a circuit produces a stable voltage synchronized with a clockpulse. The clock pulse is provided through the common timing referencefrom an external clock source (not shown). A variety of other switchablevoltage source circuits may be used instead of the illustrated circuitand many variations are possible.

The WLUD circuits include optional sleep PMOS transistors 78, one foreach circuit. The gates of the sleep switches are coupled to andcontrolled by a shared sleep enable line 78. The sleep transistordisconnects the inverter from V_(CC) thereby shutting off the word-linedrive signal. A sleep controller (not shown) can activate or deactivateany one or more of the WLUD circuits depending on the particularconnections made using the sleep enable line. In the illustratedexample, the sleep transistors are PMOS transistors with a sourcecoupled to V_(CC) and a drain coupled to the source of the firsttransistor of the corresponding inverter chain. The sleep circuitreduces power consumption and heat by disconnecting the power supplyfrom the word-line circuits. Other memory circuitry can also bedisconnected.

The two outputs of the controller of FIG. 3 are coupled to two differentswitches of the WLUD of FIG. 4. These will be referred to as the strongswitch and the weak switch, based on how much they reduce the word-linedrive circuit voltage at the word-line outputs. The strong WLUD settingis provided by a small PMOS transistor 80 embedded in each word-linedriver. Each strong WLUD transistor has a source coupled to V_(SS) and adrain coupled to the source of the first transistor of the correspondinginverter chain. When switched on, the strong WLUD transistor willconnect the power supply end of the inverter to ground, low or V_(SS).As a result, both ends of the word-line drive inverter are coupled toground although the source of the inverter is still also coupled to thedrive voltage V_(CC) though the sleep switch 76.

Using a small transistor reduces the effectiveness of this connection,so that the word-line voltage is reduced and not completely shorted out.In other words, the weak WLUD switch only partially discharges theword-line supply voltage 82. The gate is coupled to the output 46 of acomparator 42 of the controller of FIG. 3. In the illustrated example,the single comparator output is coupled to all of the WLUD circuits ofthe subarray to control all of the cells in the subarray using the samecontrol signal 46.

The strong WLUD switches can be switched on to connect both sides of theinverter to V_(SS) shorted in groups of 256 word-line drivers to providethe drive strength to discharge the word-line driver supply voltage(WLV_(CC)) 82. Through efficient use of layout space, the distributedstrong WLUD transistors incur no area overhead.

A single, large PMOS transistor 84 provides the weak WLUD setting. Theweak WLUD switch, like the strong WLUD switch, is coupled at its sourceto ground and at its drain to the source of each inverter. The gate iscoupled to the output 47 of the other comparator 43 of the controller.In the illustrated example, the single weak WLUD switch is shared by theentire 16 kB array. This keeps the area overhead to a minimum (0.1%).The larger transistor for the switch results in a larger or morecomplete discharge of the word-line supply voltage 82 when switched on.

A WLUD circuit may be made using only a weak switch or a strong switch.This provides less flexibility but reduces the complexity. Theparticular connections used to under-drive the circuit and theillustrated components can also be modified to suit differentapplications.

FIG. 5 shows simulated waveforms generated by the controller of FIG. 3and the WLUD circuit of FIG. 4 at 5 GHz (200 ps cycle) with a 1V supplyvoltage at 95° C. The particular timing and other operational parametersare provided as examples. The system can be operated at many differentspeeds and temperatures and the specific response time of the circuitcan be adapted to suit different conditions. The top graph shows theclock input as a voltage on the horizontal axis plotted against time onthe vertical axis. The clock can be used as an input 74 to the invertersof each WLUD circuit.

The middle graph shows the timing of a WL-driver wake-up signal, orsleep enable signal (wl_slpen) 78 and the output WLV_(CC) 64 withdifferent example WLUD settings. At the left end of the time axis, thesystem is in a sleep mode 92. At the end of the third falling edge 96 ofthe clock, the sleep enable signal or wake-up signal goes low. Thesystem then enters an active mode 94 on the time scale. One clock cyclelater, the word-line 96 is asserted and goes high. WLV_(CC) is restoredto the voltage level set by the WLUD circuit. Three pulses of theword-line are shown. After sufficient time is allowed to read or writeto the array, the sleep signal can be re-enabled and the word-line willbe deactivated again. As can be seen, the sleep enable signal can beused to reduce power consumption and heat in the SRAM array.

FIG. 5 shows a variety of settings identified as RA1, RA2, and RA3. Eachsetting is determined by the controller and the reference voltagesettings. In the illustrated examples, the weakest setting RA1 reducesthe word-line voltage by about 7%. The stronger RA2 setting reduces theword-line voltage by about 16% while the strongest setting RA3 providesa reduction of about 20%. In this example, the WLUD strength settings,range from 0 to 20% below V_(CC). However, other ranges can be used byadjusting the reference voltage settings and also by adjusting theparameters of the strong and weak WLUD switches depending on theembodiment. The particular choice of settings from RA1 to RA3 or anothersetting can be made based on characterization and testing and differentchoices than those illustrated can be made to suit differentapplications.

The different power levels RA1, RA2, RA3, correspond directly to thedifferent word-line under-drive voltages of FIG. 4. For RA2, P3 is onand P4 is off. For RA3, P4 and P3 are both on. The WLUD switch is off inall three cases.

FIG. 5 shows a computer system 200 incorporating features of FIGS. 2, 3,and 4 above. The computer system 200 represents an example of a systemupon which features of the present invention may be implemented. Otherelectronic devices with discrete or embedded processors including mediarecorders, media players, tablets, telephones, personal mobile devices,game consoles, set-top boxes and other devices may take a similar form.This hardware configuration is shown as an example only and a variety ofother configurations may be used instead.

The computer system 200 includes a bus or other communication conduit201 for communicating information, and a processing engine such as amicroprocessor, controller, or DSP (digital signal processor) 202coupled with the bus 201 for processing information. The sensors,controller, and read/write circuits of FIGS. 2, 3, and 4 may beimplemented in this device as shown, or in associated supporting chips.The supporting chips may be dedicated chips or dedicated portions of acontroller or input/output hub, for example.

The processor 202 includes a read/write system 203 or memory controllersuch as that shown in FIG. 4. The read/write system 203 is coupled to acache memory 205 such as an SRAM memory array as shown in FIG. 2,although other types of memory may be used. The controller circuitry ofFIG. 3 may be included in either the read/write system or in the cachememory. As mentioned above, the cache may include several memory arraysand memory sub-arrays. The read/write system and cache memory may beincluded on the same die as the processing engine or one separate die.They may be included in the same package or in a separate package.

The computer system 200 further includes a main memory 204, such as arandom access memory (RAM) or other dynamic data storage device, coupledto the bus 201 for storing information and instructions to be executedby the processor 202. The main memory also may be used for storingtemporary variables or other intermediate information during executionof instructions by the processor. The main memory may be implemented asa separate device as shown or integrated with the processor in a singlechip.

The computer system may also include a nonvolatile memory 206, such as aread only memory (ROM) or other static data storage device coupled tothe bus for storing static information and instructions for theprocessor. A mass memory 207 such as a magnetic disk or optical disc andits corresponding drive may also be coupled to the bus of the computersystem for storing information and instructions. The NVRAM and massmemory may also be combined or incorporated into the processor as asingle chip.

The computer system can also be coupled via the bus to a display deviceor monitor 221, such as a Liquid Crystal Display (LCD), for displayinginformation to a user. In addition to video, graphical and textualindications of installation status, operations status and otherinformation may be presented to the user on the display device.Typically, an alphanumeric input device 222, such as a keyboard withalphanumeric, function and other keys, or a remote control may becoupled to the bus for communicating information and command selectionsto the processor. A cursor control input device 223, such as a mouse, atrackball, a touch screen interface, or cursor direction keys can becoupled to the bus for communicating direction information and commandselections to the processor and to control cursor movement on thedisplay 221.

A communication device 225 is also coupled to the bus 201. Thecommunication device 225 may include a modem, a network interface card,or other well known interface devices, such as those used for couplingto Ethernet, token ring, or other types of physical attachment forpurposes of providing a communication link to support a local or widearea network (LAN or WAN), for example. In this manner, the computersystem may also be coupled to a number of clients or servers via aconventional network infrastructure, including an intranet or theInternet, for example. Further or alternative communication interfacesmay be provided for other types of buses, such as USB (Universal SerialBus), Firewire (i.Link or IEEE1394), Light Peak or various wirelessinterfaces.

A lesser or more equipped computer system than the example describedabove may be preferred for certain implementations. Therefore, theconfiguration of the exemplary computer system 200 will vary fromimplementation to implementation depending upon numerous factors, suchas price constraints, performance requirements, technologicalimprovements, or other circumstances. The particular nature of anyattached devices may be adapted to the intended use of the device. Anyone or more of the devices, buses, or interconnects may be eliminatedfrom this system and others may be added.

In the following description, numerous specific details are described toprovide a thorough understanding of embodiments of the invention. Oneskilled in the relevant art will recognize, however, that the inventioncan be practiced without one or more of the specific details, or withother methods, components, materials, etc. In other instances,well-known structures, materials, or operations are not shown ordescribed in detail but are nonetheless encompassed within the scope ofthe invention.

Reference throughout this specification to “an example,” “oneembodiment,” or “an embodiment” means that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least one embodiment of the present invention. Thus,appearances of such phrases in this specification do not necessarily allrefer to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

The above description of illustrated embodiments of the invention,including what is described in the abstract, is not intended to beexhaustive or to limit the invention to the precise forms disclosed.While specific embodiments of, and examples for, the invention aredescribed herein for illustrative purposes, various equivalentmodifications are possible within the scope of the invention, as thoseskilled in the relevant art will recognize. These modifications can bemade to the invention in light of the above detailed description.

The terms used in the following claims should not be construed to limitthe invention to the specific embodiments disclosed in the specificationand the claims. Rather, the scope of the invention is to be determinedentirely by the following claims, which are to be construed inaccordance with established doctrines of claim interpretation.

1. An apparatus comprising: a plurality of sensors each located near aplurality of memory cells to provide a sensor voltage; a controller toreceive the sensor voltage and provide a control signal based thereon;and a read/write assist circuit coupled to the controller to adjust aparameter applied to reading from and writing to a memory cell of theplurality of memory cells in response to the control signal.
 2. Theapparatus of claim 1, wherein the plurality of sensors are connected inparallel to produce the sensor voltage.
 3. The apparatus of claim 2,wherein the plurality of sensors produce an average voltage as thesensor voltage.
 4. The apparatus of claim 1, wherein the sensors measurethe voltage across cross-coupling nodes of a memory cell.
 5. Theapparatus of claim 1, wherein the sensors each comprise complementarypull-up and pass-gate transistors and the sensors measure the ratio of avoltage of the pull-up and the pass gate transistors.
 6. The apparatusof claim 1, wherein the sensors comprise first and second invertershaving connected internal nodes and wherein the sensors measure thevoltage at the internal nodes.
 7. The apparatus of claim 6, wherein theinverters are coupled between a source voltage and a drain voltage thatare applied to cells of the plurality of memory cells.
 8. The apparatusof claim 1, wherein the control signal comprises an on or off signal toa gate of the word-line under-drive circuit.
 9. The apparatus of claim1, wherein the controller compares the sensor voltage to a referencevoltage to switch the control signal on or off.
 10. The apparatus ofclaim 1, wherein the read/write assist circuit comprises a word-lineunder-drive circuit to reduce the drive voltage applied to a word-lineof a memory cell of the plurality of memory cells in response to thecontrol signal.
 11. The apparatus of claim 10, wherein the word-lineunder-drive circuit comprises a word-line driver circuit and a switchcontrolled by the controller to reduce the voltage supplied to theword-line drive circuit.
 11. The apparatus of claim 11, wherein theswitch is coupled between a power supply to the word-line drive circuitand a ground.
 12. The apparatus of claim 11, wherein the switch iscoupled between high and low sides of a power supply to the word-linedrive circuit.
 13. The apparatus of claim 10, wherein the word-lineunder-drive circuit receives a first control signal from the controllerto cause a first switch to reduce the power supply to a word-line drivecircuit and a second control signal from the controller to cause asecond switch to reduce the power supply to the word-line drive circuit.14. The apparatus of claim 1, wherein the sensors dynamically trackperformance variations between and among the plurality of memory cells.15. The apparatus of claim 14, wherein the controller dynamicallyadjusts settings of the read/write assist circuit in response to thesensors.
 16. A method comprising: sensing a voltage at a plurality ofsensors each located near a plurality of memory; receiving the sensorvoltage at a controller and providing a control signal based thereon;and adjusting a parameter applied to reading from and writing to amemory cell of the plurality of memory cells in response to the controlsignal.
 17. The method of claim 16, further comprising comparing thesensor voltage to a reference voltage and wherein providing a controlsignal comprises switching the control signal on or off based on thecomparison.
 18. The apparatus of claim 16, wherein adjusting a parametercomprises adjusting an amount of under-drive power of a word-lineunder-drive circuit in response to the control signal.
 19. An apparatuscomprising: a processing engine; a system bus coupled to the processingengine and to an input/output hub; a plurality of static random accessmemory cells in a memory array coupled to the processing engine as acache memory; a plurality of sensors each located near memory cells ofthe memory array each coupled in parallel to provide a combined sensorvoltage; an under-drive controller to receive the combined sensorvoltage and to provide a control signal based thereon; and a pluralityof read/write assist circuits, each coupled to the controller and to arespective memory cell the memory array to adjust a parameter applied toreading from and writing to a memory cell of the plurality of memorycells in response to the control signal.
 20. The apparatus of claim 19,wherein the read/write assist circuits comprise word-line under-drivecircuits to reduce the drive voltage applied to a word-line of a memorycell of the memory array in response to the control signal.